As the semiconductor industry introduces new generations of integrated circuits (IC's) having higher performance and greater functionality, the density of the elements that form the integrated circuits increases, and the dimensions, sizes and spacing between the individual components or elements are reduced. While in the past such reductions were limited only by the ability to define the structures photo-lithographically, device geometries having even smaller dimensions created new limiting factors. For example, for any two adjacent conductive paths, as the distance between the conductors decreases, the resulting capacitance (a function of the dielectric constant (k) of the insulating material divided by the distance between conductive paths) increases. This increased capacitance results in increased capacitive coupling between the conductors, increased power consumption, and an increased resistive-capacitive (RC) time constant. Therefore, continual improvement in semiconductor IC performance and functionality is dependent upon developing materials that comprise a dielectric film with a lower dielectric constant (low-k) than that of the most commonly used material, silicon oxide, in order to reduce capacitance.
To suit the characteristics of low-k dielectric materials, various structures and formation methods have been developed for the formation of interconnect structures. FIG. 1 illustrates a conventional formation scheme for interconnect structures. A first copper line 4 is formed in a low-k dielectric layer 2. Etch stop layer 5 is formed on low-k dielectric layer 2. A second copper line 12 is electrically coupled to copper line 4 through a via 14. The second copper line 12 and via 14 are formed in low-k dielectric layer 6. Diffusion barrier layer 10 is formed over sidewalls of a trench opening and a via opening, in which copper line 12 and via 14 are formed, respectively.
It is noted that in FIG. 1, diffusion barrier layer 10 occupies spaces in the via opening and the trench opening. Assuming copper line 12 has width T1 of 1000 Å, and diffusion barrier layer 10 has a thickness ΔT of 70 Å, the cross-sectional area of copper line 12 is reduced by about (2*70)/1000, or 14 percent. Diffusion barrier layer 10 typically includes tantalum, tantalum nitride, titanium, or titanium nitride, and typically has significantly higher resistivity than copper. Therefore, diffusion barrier layer 10 causes an increase in the resistance of a metal line, which includes copper line 12 and diffusion barrier layer 10. On the other hand, since diffusion barrier layer 10 is still conductive, the parasitic capacitance between metal line 12 and neighboring conductive features, such as copper line 16 (and the respective diffusion barrier layer 18), is not reduced. As a result, RC delay observed by copper line 12 is increased due to the formation of diffusion barrier layer 10.
Methods for overcoming the above-discussed drawbacks have been explored. For example, it has been proposed to replace diffusion barrier layer 10 with a dielectric layer. Since the distance between the neighboring metal lines are increased by 2*ΔT, the parasitic capacitance between metal lines 12 and 16 is reduced, and overall RC delay observed by copper line 12 is reduced.
The proposal of replacing diffusion barrier layer 10 with dielectric material has encountered difficulties, however. Typically, copper and dielectric layers, particularly dielectric layers having low k values, have bad adhesion. In the subsequent baking processes, copper line 12 may delaminate from dielectric diffusion barrier layer. Accordingly, new structures and/or methods for solving this problem are needed.